1. Field
This invention pertains to the field of memory systems, and more particularly, to a memory system having data inversion, and to a method of data inversion for a memory system.
2. Description
Generally, it is a goal to improve the data transfer speed of a memory system. To this end, various techniques are employed to improve the high frequency characteristics (speed) of a memory device. For some memory devices, a data inversion scheme is employed to reduce the simultaneous switching noise in the device and thereby improve the high frequency operating characteristics. An example of such a memory device and associated memory system will now be described in further detail.
FIG. 1 is a block diagram of a conventional memory system 1, having a memory device 100 and a memory controller 200.
The memory system 1 operates with a data inversion scheme, as follows. During a data write operation, the signals DM<0:3> perform a data masking operation, WDQS<0:3> operate as data strobe signals, and DIM is a write data inversion flag in indicating whether or not the data (all four data bytes) should be inverted. Meanwhile, during a data read operation, the signals RDQS<0:3> operate as data strobe signals, and DM<0:3> are read data inversion flags.
FIG. 2 shows an exemplary ball (or pin) configuration of a conventional mode memory device 100 with data inversion. As can be seen from FIG. 2, the memory device 100 includes a dedicated pin or ball 160 for the write data inversion flag DIM.
FIG. 3 shows a data processing block diagram of the memory device 100. The memory device 100 includes data processing circuit 110 for byte0, data processing circuit 120 for byte1, data processing circuit 130 for byte2, data processing circuit 140 for byte4, and memory cell array 150. In the memory device 100, each single bit of the RDQS<0:3> data strobe signals at pins 111, 121, 131 and 141, and the WDQS<0:3> data strobe signals at pins 112, 122, 132 and 142, is dedicated to one data processing unit 110, 120, 130 or 140 for processing one eight-bit byte of data for the memory cell array 150. During a data write operation, DM<0:3> at pins 114, 124, 134, and 144, masks write data for the four data processing circuits 110, 120, 130 and 140. Meanwhile, during a data read operation, each single bit of the DM<0:3> signals is dedicated as a read data inversion flag for one of the data processing unit 110, 120, 130 or 140. On the other hand, during a data write operation, DIM at pin 160 is used as a write data inversion flag for all four data bytes. Four bytes of data comprising DQ<0:31> are input/output at the input/outputs 113, 123, 133 and 143.
FIG. 4 shows a block diagram of the byte0 data processing circuit 110 of the memory device 100. The data processing circuits 120, 130, and 140 in FIG. 3 are configured similarly to data processing circuit 110. The data processing circuit 110 comprises a number of components, including data strobe signal generator 113, data control circuit 114, and the data inversion block 115. The data strobe signal generator 113 generates the read data strobe signal RDQS0. Data control circuit 114 controls data input/output during both data read and data write operations. DM0 performs two functions: it masks write data during a data write operation, and it serves to output the read data inversion flag R_FLAG0 during a data read operation. Meanwhile, DIM outputs the write data inversion flag W_FLAG during a data write operation. The data inversion block 115 performs a data inversion process during read and write operations according to the flags R_FLAG0 and W_FLAG.
FIG. 5 shows a conventional data inversion block 115. The data inversion block 115 includes the data toggle detection circuit 115-1 and the data inversion circuit 115-2. The data toggle detection circuit 115-1 detects whether the read data input from a memory cell array are inverted or not, and then outputs the read data inversion flag R_FLAG0 having the corresponding logic state. Data inversion circuit 115-2 inverts the data being written to, or read from, the memory cell array according to the logical states of the W_FLAG in a data write mode, or the R_FLAG0 in a data read mode.
The data inversion block 115 reduces the simultaneous switching noise in the input/output buffers of the memory device 100 and thereby improves the high frequency characteristics of the device.
FIG. 6 shows a conventional data toggle detection circuit 115-1. The data toggle detection circuit 115-1 compares input data DATA_INT<0:7> with a reference terminal having a reference current capability of 3.5 units. If, for example, DATA_INT<0:7> is 11111110, then the node N1 will be pulled down to a logical low state (0), and the output signal R_FLAG0 will be in a logical high state (1). Meanwhile, if DATA_INT<0:7> is 11100000, then the node N1 will be pulled up to a logical high state (1), and the output signal R_FLAGO will be in a logical low state (0). Accordingly, if the number of bits of DATA_INT<0:7> which are logically high are greater than 4 then R_FLAG0 will be logically high, while if the number of bits of DATA_INT<0:7> which are logically high are less than 4, then R_FLAG0 will be logically low.
FIG. 7 shows a conventional data inversion circuit 115-2. The data inversion circuit 115-2 includes data inverters 116-1, 116-2, 116-3, 116-4, 116-5, 116-6, 116-7, and 116-8. The data inverters 116-2, 116-3, 116-4, 116-5, 116-6, 116-7, and 116-8 in FIG. 7 are configured similarly to data inverter 116-1. During a data read operation, the READ signal closes the switches S5 and S7, while the R_FLAG0 signal closes one of the switches S1 and S2 depending upon whether the corresponding data bit is to be inverted or not. Similarly, during a data write operation, the WRITE signal closes the switches S6 and S8, while the W_FLAG signal closes one of the switches S3 and S4 depending upon whether the corresponding data bit is to be inverted or not.
FIG. 8 shows a timing diagram of a memory device with a data inversion scheme. In particular, the timing diagram of FIG. 8 shows a memory device with so-called “Burst-4” operation wherein four data bytes are written to, or read from, the memory device in a sequential burst. As can be seen from FIG. 8, read data (Q0, Q1, Q2, and Q3) are output from the memory device in sync with the rising edge of RDQS0. Meanwhile, write data (D0, D1, D2, and D3) are input to the memory device in sync with the center of the WDQS0 pulses (center strobing). Furthermore, DM0 operates as a read data inversion flag during data read operations, and to mask write data during data write operations. DIM operates as a write data inversion flag during data write operations.
Accordingly, operation of a conventional memory system 1 with a single DQS memory device 100 and a memory controller 200 has now been explained in relevant part with respect to FIGS. 1–8.
However, there are drawbacks to memory system with data inversion as described above.
For one thing, an additional pin (DIM pin) is required for the write data inversion flag. This increases the pin overhead of the memory device.
For another thing, only one write data inversion flag is provided for all of the data inputs (e.g., 32 DQ input pins) of the memory device. So, with the device and method illustrated in FIGS. 1–8, it is not possible to selectively apply data inversion to individual bytes during a data write operation. Meanwhile, applying write data inversion on a byte-by-byte basis improves the high frequency operation of the device.
Accordingly, it would be advantageous to provide a memory system and memory device having an improved data inversion function. It would also be advantageous to provide an improved method of data inversion for a memory device. Other and further objects and advantages will appear hereinafter.
The present invention is directed toward a memory system and memory device having an improved data inversion function, and an improved method of data inversion for a memory device.
In one aspect of the invention, a memory device comprises: a memory cell array that stores data; a data input/output (I/O) bus through which the data is written into and read from the memory device; a data inversion circuit that selectively inverts the data when it is written into and read from the memory cell array; and a first input/output (I/O) that carries a read data strobe when reading the data from the memory device, and that carries a write data inversion flag when writing the data into the memory device.
In another aspect of the invention, a controller adapted to write data into a memory device and to read the data out of the memory device in response to data strobe signals comprises: a data input/output (I/O) bus through which the controller writes data to, and reads data from, a memory device; and a first input/output (I/O) that carries a read data strobe when reading the data from the memory device, and that carries a write data inversion flag when writing the data into the memory device.
In yet another aspect of the invention, a memory system comprises: a memory device having a memory cell array that stores data; a controller, connected to the memory device, that writes the data into the memory device and to reads the data out of the memory device in response to data strobe signals; and a first input/output (I/O) line, between the controller and memory device, that carries a read data strobe when reading the data from the memory device, and that carries a write data inversion flag when writing the data into the memory device.